Improvements in computer performance are stalling as silicon metal-oxide-semiconductor field-effect transistors (MOSFET) approach their physical limits. To continue to drive performance while reducing power usage, attention is turning to alternative materials like carbon nanotubes (CNTs). But while CNTs offer promising attributes for transistors, the practicalities of fabricating and contacting such devices have limited their applicability to date.
Now researchers have come up with two innovations that could overcome some of these shortcomings. In the first of these, Qing Cao and colleagues from IBM Thomas J. Watson Research Center have devised a way of contacting single-walled carbon nanotube (SWNT) field-effect transistors to external metal electrodes at minute dimensions [Cao et al., Science 350 (2015) 68].
One of the major performance roadblocks facing all transistor devices is that resistance increases as the size of the contact linking the device to an external circuit shrinks. Cao and colleagues have come up with a way of bonding a Mo metal contact onto the end of a single carbon nanotube that shows no increase in resistance as its size is reduced.
‘‘We have invented a metallurgical process akin to microscopic welding that chemically binds the metal atoms to the carbon atoms at the ends of nanotubes,’’ says Cao.
The ‘welding’ process involves heating the nanotube and deposited Mo contact to 850 ?C, which together form a conductive carbide. The contact has a remarkably low resistance of 25—35 kilohm and shows no increase or barrier to hole injection as the contact size is reduced from 300 nm to less than 10 nm (Fig. 1).
‘‘Usually device contacts are done ‘from the top’ and the electrons need to flow around the corner to enter the channel. This will show as a resistance. Our idea was to contact the device from the side so that the electrons do not need to change direction to enter the channel,’’ explains Cao.
The researchers believe that the new ‘end-bonded contact scheme’, although as yet only for p-type SWNT transistors, will enable superb performance for either Si or SWNT transistors.
‘‘How to make the best contact to nanoelectronic devices has been a headache for the last 20 years,’’ says David Tomanek of Michigan State University. ‘‘But this approach has suddenly eliminated the Schottky barrier at the contact. This is a significant step forward for all nanotube and two-dimensional electronic devices.’’
Alternatively, instead of a single nanotube, a layer of single-walled carbon nanotubes (SWCNTs) can be used to create thin-film transistors (TFTs) for solution-processed, high-performance, large-area integrated circuits. Here the issue is creating stable and uniform performance in multiple devices over large areas.
Exposure to air is a particular bugbear because oxygen acts as dopant in SWCNT TFTs, changing the threshold voltage and limiting performance. So researchers at Northwestern University and the University of Minnesota have developed a means of encapsulating multiple SWCNT TFTs over large areas, enabling the fabrication of low-power static random access memory [Geier et al., Nature Nanotechnology 10 (2015) 944].
‘‘We have figured out how to stabilize the advantageous electronic qualities of SWCNTs, which was achieved through the development of new methods for doping, encapsulation, and integration of SWCNT transistors,’’ explains Mark C. Hersam of Northwestern University.
The complementary p- and n-type TFTs use a random network of semiconducting-enriched SWCNTs deposited by solution processing. Device features are patterned using standard photolithographic techniques. But after fabrication, the devices are annealed in a vacuum to remove any absorbed species and then spin-coated with photoresist in a nitrogen atmosphere to encapsulate them.
‘‘Our study is the first to identify the source of electronic property degradation and mitigate the effects using thin encapsulation layers,’’ says Hersam. ‘‘These developments have allowed the demonstration of the most complex CMOS circuits based on SWCNTs to date.’’
The team integrated their encapsulated SWCNT devices into fully functional CMOS SRAM circuits. The devices operate at 2 V and are fully compatible with standard digital logic, points out Hersam. But this achievement is just a demonstration of the possibilities.
‘‘This work is very much a platform for further integration,’’ Hersam told Nano Today. ‘‘We plan to take this work forward into more complex functional systems that are integrated on flexible substrates... and explore applications that would benefit the most from low temperature processing and reliability over large areas.’’
Aaron D. Franklin of Duke University believes the approach shows promising performance for applications.
‘‘This is precisely the type of work that we need to see more of,’’ he told Nano Today. ‘‘Without question, these results provide considerable progress in understanding how thin films of carbon nanotubes, having no complex or costly alignment procedures, can yield complementary circuits in one of the most important structures, the SRAM cell.’’
This article was originally published in Nano Today (2015), doi:10.1016/j.nantod.2015.10.002
Figure 1 False-colored scanning electron microscope image showing a set of end-contacted nanotube transistors fabricated on the same nanotube with contact geometries ranging from sub-10 nm to 60 nm. (Credit: IBM Research.)