This paper reviews the properties of the SOI wafers fabricated using the Smart Cut™ technology, with ultra-thin body and buried oxide (BOX) required for the FD-SOI CMOS platform. It focuses on the parameters that require specific attention for this technology, namely, the top silicon layer thickness uniformity and buried oxide reliability. The first one is linked to the threshold voltage variability and the second to the active role played by the BOX when a back-bias is used. An overview of the specific process optimization and metrology developed to achieve the targeted specifications is given.
This article originally appeared in Solid-State Electronics, 117, 2016, pages 2-9.
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