Schematic of a 5 nm CNT FET showing the device in the off state.
Schematic of a 5 nm CNT FET showing the device in the off state.
Schematic of a 5 nm CNT FET showing the device in the off to on state.
Schematic of a 5 nm CNT FET showing the device in the off to on state.
Schematic of a 5 nm CNT FET showing the device in the on state with a single electron responsible for the switch.
Schematic of a 5 nm CNT FET showing the device in the on state with a single electron responsible for the switch.

Transistors based on single semiconducting carbon nanotubes (CNTs) are pushing performance to the ultimate physical limits, as set out by quantum mechanics. Researchers from Peking University believe that they have come closer than ever before to these fundamental limits of device physics with their CNT transistor [Qiu et al., Science 355 (2017) 271].

Silicon complementary metal-oxide semiconductor (CMOS) technology, which has followed Moore’s law of decreasing dimension with increasing performance for decades, is reaching its physical limit. To go beyond the 10 nm technology node, new transistor designs such as those based on CNTs will be needed.

Lian-Mao Peng and his team have fabricated CMOS field-effect transistors (FETs) based on semiconducting single-wall CNTs that perform better than their Si counterparts at the same scale. Each device is made up of four components: a conducting channel comprising a single semiconducting SWCNT; a gate insulated from the CNT channel by an ultra-thin dielectric film; graphene drain and source contacted to the CNT channel to provide a transport path for charge carriers.

“The CNT FETs we constructed are the smallest and highest performing FETs,” says Peng. “CNT FETs can be used as electric switches or building blocks for constructing 2-binary logical integrated circuits.”

The team’s 10 nm CNT CMOS FETs perform better and have lower power consumption than the best 14 nm Si CMOS FETs.

“But we also wanted to know how close can we approach fundamental limits set by quantum principles,” he explains, “and what ultimate size and performance a real transistor can have; as well as how far we can go beyond Si technology or Moore's law.”

The answer, it seems, could be the team’s 5 nm CMOS FET, which approaches the quantum limit of 2-binary switching. In other words, just a single electron is responsible for each switching operation in the device.

"These findings indicate that CNT FETs can perform much better than Si CMOS FETs at similar size, and thus have the potential to extend Moore’s law beyond Si for many years to come and to the physical limits imposed by quantum principles,” says Peng.

CNT FETs could form the building blocks of integrated circuits with much higher performance and lower power dissipation than state-of-the-art Si technology. The unique attributes of CNTs mean that this technology could enable a new generation of flexible and transparent electronic devices. However, there are still hurdles to overcome, admits Peng.

“The approach we used – individual semiconducting CNTs with known properties – is suitable for building prototypical devices and circuits, but is not a practical approach for industry applications,” he says.

Instead, suggests Peng, high-quality semiconducting CNT films could enable the fabrication of high-performance transistors and large scale ICs on the wafer scale.

Aaron D. Franklin of Duke University believes the work is another significant milestone on the path towards CNT transistor technology.

“Although it’s not the type of work that resolves the materials processing challenges, it provides key evidence of how aggressively scalable the size of these devices can be in comparison to Si transistors,” he explains. “Pushing down to a 5 nm gate length without incurring major short channel effects (loss of control in the device), is very impressive.”

This article was originally published in Nano Today (2017), doi: 10.1016/j.nantod.2017.02.004.